Receiver Card Requirements

[This is preliminary documentation and subject to change.]

The receiver card's interface with the computer should:

• Provide a mechanism for moving data into the computer and for specifying the destination for that data in computer memory, preferably through bus mastering.
• Control the tuner and retrieve tuner information.
• Control decoding of video, audio, and other data.
• Control the different Viterbi or other decoding rates used by the digital broadcast network.
• Control what packet identifiers (PIDs) are received and what data is routed to the computer.
• Retrieve status information about errors and control error correction.
• Satisfy the requirements for receiving MSBDN packets, which can require additional hardware beyond that required for audio and video. For more information on receiving MSBDN packets, see the MSBDN Receiver section of the Broadcast Architecture Device-Driver Kit (DDK), part of the Windows 98 DDK.
• Support of at least five PIDs simultaneously. Support of eight is recommended.
• Perform one of the two following tasks:
  • Present an advancing 27 megahertz register, a register containing the last-received system clock reference (SCR) or other reference time stamp, and a register containing the value of the 27 megahertz register when the last SCR was received.
  • Generate an interrupt immediately upon receipt of each SCR and have that SCR read through the PCI bus.
• Perform PCI bus mastering with support for scatter/gather memory access and unaligned, odd-byte memory transfers. This requirement includes support for time-critical MPEG packets of 127 bytes and less.

The following illustration shows the receiver card's internal and external data flow. In this illustration, bps is bits per second, QPSK is Quadrature Phase Shift Keying (a method of encoding digital data in an analog signal), DEMOD is demodulator, DES is Data Encryption Standard, and Mbps is megabits per second.