4.6. Configuring Card Resource Usage

Plug and Play cards support the following registers which are used for configuring the card's standard ISA resource usage per logical device.

Memory Address Base registers (up to four non-contiguous ranges)
I/O Address Base registers (up to eight non-contiguous ranges)
Interrupt Level Select registers (up to two separate interrupt levels)
DMA Channel Select registers (up to two DMA channels )

These registers are read/write and always reflect the current operation of all logical devices on the Plug and Play card. If a resource is not programmable, then the configuration register bits are read-only.

4.6.1. Order of Configuration Reads

Resource data is read from each Plug and Play card that describes how many logical devices are on the card as well as the resource requirements for each logical device. Any of the configuration registers that are programmable must be programmed into the logical device through the card's Plug and Play register interface.

Logical device's configuration registers are programmed by first writing the logical device number to the Logical Device Number register. The logical device number is determined by the order in which logical devices are read from the card's resource data. The first logical device read is number 0, the next is number 1, and so on. Logical devices may be programmed in any order.

After the logical device is selected, configuration registers are programmed by writing the proper values to the Plug and Play register interface. The Plug and Play register that must be written for each resource is determined by the order in which each resource is read from the Resource Data. For example, a logical device has the following Resource Data structure:

     TAG Logical Device
          TAG Memory Descriptor          (becomes memory descriptor 0)
          TAG Memory Descriptor          (becomes memory descriptor 1)
          TAG I/O Descriptor                   (becomes I/O descriptor 0)
          TAG Start DF                         (dependent function)
               TAG I/O Descriptor        (becomes I/O descriptor 1)
               TAG Int Descriptor        (becomes interrupt descriptor 0)
           TAG Start DF                       (next set of dependent resources)
               TAG I/O Descriptor        (I/O descriptor 1)
               TAG Int Descriptor        (Interrupt descriptor 0)
          TAG End DF                                 (end of resource dependencies)
     TAG END

This example shows a logical device that needs two independent memory ranges and one independent I/O range. They are defined as Memory Descriptor 0, Memory Descriptor 1 and I/O Descriptor 0 based on the order they were read from the Resource Data structure. Memory Descriptor 0 is programmed at Plug and Play registers 0x40 - 0x44, Memory Descriptor 1 is programmed at Plug and Play registers 0x48 - 0x4C and I/O Descriptor 0 is programmed at Plug and Play registers 0x60 - 0x61. These resource data formats are fully defined in a following section. It is recommended that all independent descriptors appear before any dependent functions. This may simplify the mapping of resource descriptors to configuration registers in some hardware implementations.

The Resource Data for this logical device next calls out a dependent function of one I/O port range and one interrupt. These become I/O descriptor 1 and interrupt descriptor 0 because they are the second I/O and first interrupt resources read for this logical device. The next dependent function entry still represents I/O descriptor 1 and interrupt descriptor 0.

These configuration registers may be programmed in any order, only the register bindings are defined based on the order they are read from the Resource Data structure.

4.6.2. Resource Programming

Plug and Play cards are programmed by sending the card a Wake[CSN] command with the write data set to the card's CSN. This will force the one card with the matching CSN into the Config state and force all other cards into the Sleep state. Next, the logical device to be programmed is selected by writing the logical device number to the Logical Device Number register. If the card has only one logical device, this step may be skipped.

Resource configuration for each logical device is programmed into the card using the registers for I/O, memory, IRQ, and DMA selection defined in Appendix A. Each and every resource requested by a logical device must be programmed, even if the resource is not assigned. Each resource type is described below.

Memory Configuration - Memory space resource use is programmed by writing the memory base addressto the memory base address registers. Next, the memory control is written with the correct 8/16/32 bit memory operation value and the decode select option. If the memory decode option was set to range length, then the range length is written to the memory upper limit/range length registers. If the memory decode option was set to upper limit, then the upper limit memory address is written to the upper limit/range length register. If no memory resource is assigned, the memory base address registers must be set to zero and the upper limit/range length registers must be set to zero.
I/O Space Configuration - I/O space resource use is programmed by writing the I/O base address[15:0] to the I/O port base address registers. If a logical device indicated it uses 10-bit I/O space decoding, then bits [15:10] of the I/O address are not implemented on the card. If no I/O resource is assigned, the I/O base address registers must be set to zero.
Interrupt Request Level - The interrupt request level for a logical device is selected by writing the interrupt request level number to the Interrupt Level Select register. This select number represents the number of the interrupt on the ISA bus. The edge/level and high/low active state of the interrupt must be written to the Interrupt Request Type register. If no interrupt is assigned, the Interrupt Level Select register must be set to 0. The IRQ2 signal is used internally by the 8259 interrupt controller and is not a valid IRQ selection for Plug and Play cards. To indicate this interrupt channel, cards should report IRQ9. To select this interrupt channel, the Interrupt Level Select register must be set to 9, not 2.
DMA Channel - The DMA channel for a logical device is selected by writing the DMA channel number to the DMA Channel Select register. The select number represents the number of the DRQ/DACK channel on the ISA bus. If no DMA channel is assigned, this register must be set to 4.

The last step in the programming sequence is to set the logical device's activate bit. This forces the logical device to become active on the ISA bus at its assigned resources. When finished programming configuration registers, all cards must be set to the Wait for Key state.